An integrated circuit can have millions of circuit features, such as transistors and capacitors, formed on a chip. Some ICs include an array of memory cells for storing information. To access the memory cells, addressing circuitry such as decoders, drivers and sense amplifiers (generally referred to as support circuitry) are provided. The chip is separated into array and support regions in which memory cells and support circuitry are respectively located. One type of memory cell 105 includes a trench capacitor coupled to a vertical transistor 130, as shown in FIG. 1. Such types of memory cells are described in, for example, Weis et. al., “A Highly Cost Efficient 8F2 DRAM Cell with a Double Gate Vertical Transistor Device for 100 nm and Beyond”, International Electron Device Meeting IEDM, Washington (2001), which is herein incorporated by reference for all purposes. The capacitor is formed in a lower portion 111a of a trench created in a substrate 106. The upper portion 111b of the trench comprises a gate 133 of the vertical transistor. A trench top oxide 148 is located in the trench between the transistor and capacitor, providing isolation between the two. The capacitor is coupled to the transistor via a buried strap 174 and buried diffusion region 132. A gate oxide 135 lines the trench sidewall in the upper portion of the trench. A diffusion region 131 is located on the substrate surface surrounding the trench. A wordline is coupled to the gate and a bitline is coupled to the diffusion region.
Unfortunately, circuit requirements for the memory cells and support circuitry are different. For example, current integration processes for vertical array memory cells result in an insufficient active area corner rounding for support devices. This can undesirably lead to performance degradation for support devices.
From the foregoing discussion, it is desirable, to provide an integration process which can accommodate for the needs of the array and support devices.